In recent years, a MIS LSI is desired to have more high performance and more high density integration. In order to realize these requirements, semiconductor technologies, such as miniaturizing a gate size of a MISFET and suppressing a lateral diffusion of impurities in a source-drain region, have been developed in accordance with a scaling rule.
Decreasing the gate size of the MISFET by the miniaturization generally involves a short channel effect on MISFET characteristics by spreading a depletion region near a drain region of a silicon substrate. The short channel effect is greatly influenced by extension regions formed in a source-drain structure of the MISFET.
Such the extension regions are formed in following steps. Conductive impurities are introduced into the silicon substrate by using ion implantation employing the gate electrode as a mask, after forming a gate electrode. Subsequent thermal annealing activates the implanted impurities. The impurities deeply and laterally diffuse into the silicon substrate. The impurity diffusion is also accompanied by thermal annealing in following steps of the MISFET process. Accordingly, the miniaturization of the gate length leads to the short channel effect.
In order to solve this problem, a notch-type gate electrode has been proposed. For example, Japanese Patent Publication (Kokai) No.2003-332567 discloses a method of fabricating a semiconductor device having a notch-type gate electrode. In the notch-type gate electrode, the gate electrode having a longer gate length than a predetermined gate length is formed first. The upper side wall of the gate electrode is covered with a mask, subsequent etching of the lower side wall of the gate electrode shorten the length of the gate electrode. The length of the gate electrode is defined at the shortened length of the lower gate electrode portion.
On the other hand, the ion implantation forming the extension region is performed employing the upper gate electrode as a mask, thus, the channel region of the MISFET is formed in the surface of the silicon substrate beneath the upper gate electrode rather than in lower gate electrode. As a result, a channel length suppressing the short channel effect can be formed in the surface region beneath the notch-type gate electrode. The miniaturization of the MISFET can be realized by the notch-type gate electrode.
However, there are some problems in the notch-type gate electrode structure. For example, it is difficult to control the gate electrode length with high precision. Because the lower side wall of the gate electrode is laterally etched, the gate electrode length is determined by the etching conditions, such as etching rate and etching time. That is, the difference between the length of the lower gate electrode and that of the upper gate electrode cannot be precisely controlled. Therefore, the MISFET with sufficient characteristics cannot be obtained in a case of the notched-type gate electrode.
Moreover, an etching rate of the gate electrode near an interface with a gate insulating layer becomes comparatively slow, and accordingly, forming the lower gate electrode with a straight shape is more difficult. Furthermore, as the processing steps of forming the side wall mask on the side wall of the upper gate electrode becomes comparatively long, a cost of fabricating the MISFET becomes comparatively high.